4 New Products/Ideas Will Allow Significant Energy Savings And Performance Improvements For Upcoming LTE Devices

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 So last year physorg.com had a story about saving 50% power consumption just by enhancing content strategies. I’ve been keeping my eyes on that one, therefore when I saw these, my triggers went off. I have about 4 technologies that are not earth shattering but each add up to dramatically slice power consumption for mobile devices. Here goes..

 BTW, this latest batch of technology is fundamental and is useful for all 4G LTE devices being used in most any way.

Firstly. there is a company called Quantance that has introduced a seriously kick butt power amplifier device for UEs. Their Q845 is a single chip 0.18μm component that enables Envelope Tracking (ET) for power amplifiers (PA) therefore, when combined with a relatively efficient PA component the effective power efficiency can approach 50% vs typical 35% seen in today’s designs. Here is their nifty graphic that shows the benefits: 

Quantance calls their ET technology qBoost. This is a significant improvement for LTE mobile radios. Don’t forget that this ET approach improves linearity of the PA. This will be realized as greater dBs TX power and improved Error Vector Magnitude (EVM) for greater throughputs in the uplink at the reduced power.

 

 

 

 

 

 

 

 

 

 

 

 

Second, let’s consider the improvement researchers Xinyu Zhang and Kang G. Shin of the University of Michigan outlined…That was a strategy called E-MiLi (Energy-Minimizing idle Listening.)  

A new “subconscious mode” for smartphones and other WiFi-enabled mobile devices could extend battery life by as much as 54 percent for users on the busiest networks. 

 This was targeted for WiFi and saves around 44% of total radio power. Their paper is here

Lastly there is Dockon. Dockon explains their technology best as:

DockOn’s CPL antenna technology is based on the concept of increasing efficiency and bandwidth by exciting magnetic and electric radiators together from a single feed location. This concept, referred to as “compound antenna theory”, has been perfected by DockOn for use in a wide variety of commercial applications and implemented on a variety of substrates including rigid/flex PCB, stamped metal and Laser Direct Structuring (LDS).

Their white paper can be found here.

So overall this increased antenna efficiency will increase the amount of RF power coming into and out of the antenna, therefore improving performance and battery life (less TX adjusting required since RX is better.)

 Beyond the constant improvements in processors that we are hearing about, both ARM designs and graphics processors, there is a new memory standard , double data rate type four synchronous dynamic random-access memory (DDR4). Note, the standards organization, JEDEC defines this standard. 

This memory is faster for greater performance and offers a theoretical savings of 20% overall. Samsung is now sampling these modules for servers etc and so the mobile devices seem to be more like 2013ish, but nonetheless an important technology to keep our eyes on. 

There is the simple list of 4 complementary technologies that can offer power savings in devices beyond the traditional process shrinks that are now expected in the processor domain. 

Good day..

Links: DockonJEDECQuantanceUniversity of Michigan, Wikipedia

 

 

JEDEC DDR4

With publication forecasted for mid-2012, JEDEC DDR4 will represent a significant advancement in performance with reduced power usage as compared to previous generation technologies. When published, the new standard will be available for free download at www.jedec.org.
DDR4 is being developed with a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. Its speed, voltage and architecture are all being defined with the goal of simplifying migration and facilitating adoption of the standard.
A DDR4 voltage roadmap has been proposed that will facilitate customer migration by holding VDDQ constant at 1.2V and allowing for a future reduction in the VDD supply voltage. Understanding that enhancements in technology will occur over time, DDR4 will help protect against technology obsolescence by keeping the I/O voltage stable.
The per-pin data rates, over time, will be 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second. With DDR3 exceeding its expected peak of 1.6 GT/s, it is likely that higher performance levels will be proposed for DDR4 in the future. Other performance features planned for inclusion in the standard are a pseudo open drain interface on the DQ bus, a geardown mode for 2667 Mhz data rates and beyond, bank group architecture, internally generated VrefDQ and improved training modes.
The DDR4 architecture is an 8n prefetch with bank groups, including the use of two or four selectable bank groups. This will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each of the unique bank groups. This concept will improve overall memory efficiency and bandwidth, especially when small memory granularities are used.
Additional features in development include:
  • Three data width offerings: x4, x8 and x16
  • New JEDEC POD12 interface standard for DDR4 (1.2V)
  • Differential signaling for the clock and strobes
  • New termination scheme versus prior DDR versions: In DDR4, the DQ bus shifts termination to VDDQ, which should remain stable even if the VDD voltage is reduced over time.
  • Nominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin
  • Burst length of 8 and burst chop of 4
  • Data masking
  • DBI: to help reduce power consumption and improve data signal integrity, this feature informs the DRAM as to whether the true or inverted data should be stored
  • New CRC for data bus: Enabling error detection capability for data transfers – especially beneficial during write operations and in non-ECC memory applications.
  • New CA parity for command/address bus: Providing a low-cost method of verifying the integrity of command and address transfers over a link, for all operations.
  • DLL off mode supported
To facilitate comprehension and adoption of the DDR4 standard, JEDEC is planning to host a DDR4 Technical Workshop following the publication of the standard. More information and details will be announced coincident with publication.

Looking towards the future, JEDEC’s JC-42 Committee for Solid State Memories stands at the forefront of the ongoing effort to produce next generation memory device standards.